An embodiment of the invention relates to the field of the electronic design automation, EDA/computer aided design, CAD of large scale integrated circuits (ICs), and particularly to laying out or routing power rail structures for a circuit cell that is used to design such integrated circuits. Other embodiments are also described.
Computer-aided cell-based design has been developed for quickly designing large scale ICs such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as Standard Cell and Gate Array use different types of such building blocks, although the term “standard cell” as used here is intended to encompass both types. In a Standard Cell design, each distinct cell in a library may have unique geometries of active, gate, and metal levels. With Gate Arrays however, each cell shares the same basic building block, called a core cell that consists of fixed active and gate level geometries. Thus, different gate array cells are implemented using only metal interconnections between the active and gate elements of one or more core cells. Examples of a standard cell include a NAND gate, a NOR gate, a flip flop, and other similar logic circuits. A designer may select particular cells from a library of cells and insert them into a design. The library includes cells that have been designed for a given IC manufacturing process (e.g., complementary metal oxide semiconductor, CMOS, fabrication). The cells generally do not change from one design to the next, but the way in which they are interconnected will, to achieve the desired function in a given design. By being able to select the cells from the library and simply place them into the design, the designer can quickly implement the function without having to custom design the cells. He will thus have a certain level of confidence that the function will likely work as intended, when the integrated is actually manufactured, without having to worry about the details of the individual transistors that make up each cell.
The routing layers, such as metal layers, used in IC design have various routing elements such as wire (or line) and via elements. These perform at least two functions: they connect individual transistors to make up a cell, including supplying power to the cell, and they connect cells to each other globally to implement the desired function of the integrated circuit. The EDA/CAD software takes a design netlist of interconnected cells, and automatically places cells and routes the connections between them on a typical, square grid that overlays a region of the IC die (to be manufactured). The placement and routing of the netlist components has to comply with certain design rules, so that inevitable manufacturing process variations in the IC die can be tolerated.